The present invention relates generally to integrated circuits, and more particularly, to an integrated circuit with test circuitry.
Integrated circuits (ICs) may have manufacturing defects caused by, for example, contamination by dust particles during fabrication, which can cause the ICs to malfunction. Thus, testing ICs to detect manufacturing defects is essential. Design for Test (DFT) techniques add testability features to ICs to enable identification of manufacturing defects. DFT techniques allow an Automatic Test Equipment (ATE) to execute various fault tests on ICs. The ATE uses test patterns generated by test pattern generators, such as Automatic Test Pattern Generators (ATPGs), Pseudo-Random Pattern Generators (PRPGs), and the like, to detect faults.
Scan testing is a well-known DFT technique. During scan testing, shift and capture operations are performed, in which test patterns are shifted through the scan chain. A flat shift operation on large designs is not feasible due to tester pin limitations and power considerations. For this reason, today's ICs typically are divided into multiple partitions, where each partition can do shift operations independently, and each partition includes multiple scan chains.
Partitioned scan requires partitions to be isolated from each other through mechanisms like x-blocking where all inputs of the partition are driven from a node internal to the partition (INTEST mode or internal scan testing). After covering partitions individually the inter-partition paths/nodes are covered using scan wrappers (EXTEST mode or external scan testing). INTEST is performed on a functional path within a partition, and EXTEST is performed on a functional path between two partitions.
Referring to FIG. 1, a schematic block diagram of a conventional IC 100 that is operable in INTEST and EXTEST modes is shown. The IC 100 includes first and second partitions 102 and 104. The first partition 102 includes a first flip-flop 106, a first combinational circuit 108, a first multiplexer 110, and a first scan chain 112. The second partition 104 includes a second multiplexer 114, a second combinational circuit 116, a compression circuit 118, a second scan chain 120, and a second flip-flop 122.
The first flip-flop 106 has receives a first input signal (VIN_1), a clock signal (VCLK), a scan enable signal (VSE), and outputs a first output signal (VOUT_1). The scan enable signal indicates either a shift operation or a capture operation. The first combinational circuit 108 is connected to the output of the first flip-flop 106 for receiving the first output signal and generating a second output signal (VOUT_2). The first scan chain 112 receives a scan input signal (VSI) and generates a scan output signal (VSO) during the shift operation, where the scan input signal is a test pattern provided to the first scan chain 112 by an ATE (not shown).
The first multiplexer 110 is connected to the first combinational circuit 108 for receiving the second output signal, and to a flip-flop of the first scan chain 112 for receiving a scan vector initialization signal (VINIT). A select terminal receives an EXTEST mode control signal (VEXTEST_MODE), and the first multiplexer 110 outputs one of the second output signal and the scan vector initialization signal as a third output signal (VOUT_3). The scan vector initialization signal indicates a test pattern being applied to the IC 100 in the EXTEST mode. The first scan chain 112 generates the scan vector initialization signal during the shift operation. The EXTEST mode control signal indicates whether the IC 100 is in the EXTEST mode. A path between the first and second scan chains 112 and 120 (hereinafter referred to as “functional path between the first and second partitions 102 and 104”) is tested during the EXTEST mode.
The second multiplexer 114 receives the third output signal and a second input signal (VIN_2), and outputs a fourth output signal (VOUT_4) based on a select input, which is an inverted version of the EXTEST mode control signal (VINV_EXTEST_MODE). The second combinational circuit 116 is connected to the output of the second multiplexer 114 for receiving the fourth output signal and generating a fifth output signal (VOUT_5). The second flip-flop 122 is connected to the second combinational circuit 116 for receiving the fifth output signal, and outputs a sixth output signal (VOUT_6).
The compression circuit 118 is connected to the second multiplexer 114 for receiving the fourth output signal and generating a compressed output signal (VCOMP_OUT). The compression circuit 118 provides the compressed output signal to a flip-flop of the second scan chain 120 during the capture operation.
The second scan chain 120 receives the compressed output signal from the compression circuit 118 during the capture operation. The second scan chain 120 also receives a test input signal (VTEST_IN) during the shift operation. The test input signal is a test pattern provided to the second scan chain 120 by the ATE. The second scan chain 120 generates a test output signal (VTEST_OUT) during the shift operation, thereby testing the functional path between the first and second partitions 102 and 104. The test output signal is compared with a known value to determine if the IC 100 contains a fault. However, this method adds muxes to the functional path, which impacts the timing of functional signals by adding propagation delays. Further, the test logic does not facilitate testing the path between the first and second flip-flops 106 and 112. It would be advantageous to have a testable IC that reduces the impact on the propagation delay of a functional path between partitions.